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Freescale Semiconductor /MK70F15WS /DDR /CR43

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Interpret as CR43

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0P2RDCNT0RESERVED0 (00)RP20RESERVED0 (00)WP20RESERVED

WP2=00, RP2=00

Description

DDR Control Register 43

Fields

P2RDCNT

Port 2 Read command Count
RESERVED

Reserved
RP2

Read command priority Port 2

0 (00): Highest

1 (01): -----

2 (10): -----

3 (11): Lowest
RESERVED

Reserved
WP2

Write command priority Port 2

0 (00): Highest

1 (01): -----

2 (10): -----

3 (11): Lowest
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data